Projects & Portfolio

The Challenge

The client needed a 3.3 kW OBC with wide input voltage range (90–270 V AC), PFC stage for unity power factor, isolated DC output for a 72 V lithium-ion battery pack, and compliance with BIS IS 17017 and AIS-138 standards. The unit had to fit within a constrained volume and survive Indian road vibration profiles.

Our Approach

We designed a two-stage architecture: a bridgeless totem-pole PFC front end followed by an LLC resonant DC-DC converter. The LLC stage was optimised for zero-voltage switching across the full load range. Custom magnetics were designed for minimum loss. The control firmware was developed in-house on a DSP platform.

Outcome

The OBC achieved 94.2% peak efficiency and passed BIS certification on first attempt. The design was subsequently licensed to the client for in-house production. The firmware source code and full design documentation were delivered as part of the engagement.

Technical Specifications

The Challenge

The programme required a high-speed signal processing board capable of ingesting ADC data at 1 GSPS over JESD204B, performing real-time pulse compression and MTI filtering, and outputting processed data over 10G Ethernet — all within a strict SWaP (size, weight, and power) budget.

Our Approach

We selected a Xilinx UltraScale+ FPGA for the processing core. The PCB was designed as a 16-layer stackup with controlled impedance for JESD204B and DDR4 interfaces. RTL was developed in VHDL with formal verification of the critical DSP pipeline. Power integrity analysis was performed using Ansys SIwave.

Outcome

The platform achieved the target processing latency of under 10 µs for a 1024-point pulse compression kernel. The design passed signal integrity validation and is currently in system integration testing with the radar front end.

Technical Specifications

The Challenge

The client required a low-noise, high-dynamic-range RF front end with a noise figure below 3 dB, image rejection better than 50 dBc, and spurious-free dynamic range (SFDR) exceeding 70 dBc. The module had to operate across -40°C to +70°C and survive MIL-STD-810 environmental testing.

Our Approach

We designed the receive chain using a GaAs LNA MMIC for the first stage, followed by a double-balanced mixer and IF amplifier chain. The PCB was designed on Rogers RO4350B substrate with microstrip transmission lines. All passive components were characterised on a VNA before assembly. EM simulation was performed in Ansys HFSS.

Outcome

The module achieved a system noise figure of 2.8 dB and SFDR of 74 dBc. It passed MIL-STD-810G environmental qualification and was delivered with full S-parameter characterisation data across temperature.

Technical Specifications

The Challenge

The ECU had to manage 24 V DC power distribution across 12 load channels with individual overcurrent protection, interface with 16 analogue sensors, communicate over dual-redundant CAN bus, and survive 40g mechanical shock and MIL-STD-461F EMI qualification.

Our Approach

We designed the ECU around a safety-rated microcontroller with hardware watchdog and redundant power supply rails. Load switching was implemented using automotive-grade high-side drivers with current sensing. The PCB was designed for conformal coating and potting. Firmware was developed to MISRA-C guidelines.

Outcome

The ECU passed all qualification tests including 40g shock, MIL-STD-461F, and 1000-hour HALT testing. It was delivered with full FMEA documentation and source code escrow as required by the client.

Technical Specifications

The Challenge

The programme required a hardware shim that could translate between the legacy radio's parallel data interface and a modern serial protocol, implement a frequency-hopping schedule in hardware, and do so without modifying the existing radio firmware — a contractual constraint.

Our Approach

We designed an FPGA-based interface module that intercepts the legacy parallel bus, implements the hopping schedule in RTL, and presents a clean UART/SPI interface to the C2 system. The module includes a hardware security element for key storage. All design work is conducted under a classified NDA.

Outcome

Phase 1 (hardware design and bench validation) is complete. Phase 2 (system integration and field trials) is ongoing. Further details are restricted under the programme NDA.

Technical Specifications